RISC (Reduced Instruction Set Computer) advocates for simple, single-cycle instructions with a focus on executing a larger number of simple operations efficiently. CISC (Complex Instruction Set Computer) provides complex multi-cycle instructions that can perform sophisticated operations in a single instruction.

The distinction has blurred because modern CISC processors like x86 internally decode complex instructions into simpler micro-operations (μops) that execute on a RISC-like core. Meanwhile, RISC architectures like ARM have added complexity instructions and larger micro-op caches. The result is that both approaches deliver similar performance through different means—x86 hides complexity in decoder hardware while ARM exposes simplicity through the instruction set.

The fetch-decode-execute cycle is the fundamental operation of any CPU. First, the fetch phase retrieves the next instruction from memory using the address in the program counter (PC) register, then increments the PC. Second, the decode phase interprets the instruction bits to determine what operation to perform and which operands to use. Third, the execute phase performs the actual computation—accessing registers, performing ALU operations, or memory reads/writes.

The ISA defines exactly what each phase must do: what instruction encoding looks like, how many operands each instruction takes, which registers exist, and what operations the ALU must support. Different ISAs have different fetch widths (how many bytes per cycle), decode complexity, and execution unit capabilities, but all must implement this basic cycle.

Addressing modes specify how instructions locate their operands. Common modes include immediate (constant values embedded in the instruction), register direct (value in a register), and various memory addressing forms like direct (absolute address), indirect (register contains address), and indexed (base plus offset).

Different architectures support different sets based on their design philosophy. RISC architectures often limit addressing modes to reduce instruction complexity and keep decode simple—ARM primarily supports immediate and register direct, plus base-plus-offset for memory access. CISC architectures like x86 support many addressing modes to allow complex memory operand specifications in single instructions. The trade-off is decode complexity versus instruction flexibility.

x86 uses strong memory ordering, meaning stores are not reordered with other stores and loads are not reordered with other loads or stores. This makes porting concurrent code from x86 to ARM dangerous—code that appears correct due to implicit ordering can fail on ARM's weak ordering.

ARM uses weak ordering where loads and stores can be reordered by the hardware for performance. This means a load can be reordered with a preceding store, potentially reading stale data. Developers writing lock-free code or concurrent data structures must use explicit memory barriers (DMB, DSB on ARM; MFENCE on x86) to enforce ordering when required.

The stack pointer (SP) always points to the current top of the stack, where the next push will store data. It automatically adjusts as values are pushed and popped during function calls, returns, and local variable allocation.

The base pointer (BP), also called frame pointer, provides a stable reference point within a function's stack frame. While SP moves during execution, BP remains fixed throughout the function, making it easy to locate function parameters and locals at known offsets from BP. This is essential for debuggers to perform stack unwinding and for exception handling. Modern compilers can omit frame pointers with -fomit-frame-pointer optimization when frame pointers aren't needed for debugging.

Instruction pipelining overlaps execution of multiple instructions by dividing execution into stages (fetch, decode, execute, memory, write-back). While one instruction is in stage 2, the next can be in stage 1.

Major hazards include:

• Structural hazards: Hardware cannot support all combinations of instructions in pipeline simultaneously (e.g., single memory port)
• Data hazards: Instruction depends on result of previous instruction still in pipeline (RAW, WAR, WAW)
• Control hazards: Branch decision affects which instruction fetches next; misprediction costs 10-20 cycles

Solutions include forwarding paths, branch prediction, and out-of-order execution to hide dependencies.

RISC (Reduced Instruction Set Computer) advocates simple, single-cycle instructions with emphasis on executing a large number of simple operations efficiently. CISC (Complex Instruction Set Computer) provides complex multi-cycle instructions that can perform sophisticated operations in a single instruction.

The distinction has blurred because modern CISC processors like x86 internally decode complex instructions into simpler micro-operations (μops) that execute on a RISC-like core. Meanwhile, RISC architectures like ARM have added complexity instructions and larger micro-op caches. The result is that both approaches deliver similar performance through different means.

A calling convention defines how functions exchange data: parameter passing (registers vs stack), return value location, caller/callee-saved register handling, and stack frame layout.

Common conventions include:

• System V AMD64 ABI: Parameters in RDI, RSI, RDX, RCX, R8, R9, then stack; return in RAX
• Microsoft x64 ABI: Parameters in RCX, RDX, R8, R9; shadow space on stack
• ARM64 AAPCS: Parameters in X0-X7; return in X0

Mismatches between caller and callee conventions cause subtle bugs—wrong values returned, registers clobbered, crashes on external library calls. Compiler and language support handle this, but mixing assembly with high-level code requires explicit knowledge.

The instruction fetch stage retrieves instructions from memory using the Program Counter (PC). On modern CPUs, this involves:

1. Fetch address calculation: PC points to the next instruction. For sequential flow, PC = PC + instruction_length. For branches, the target comes from the branch predictor.
2. L1 I-cache lookup: The instruction fetch unit sends the PC to the L1 instruction cache. If hit (typical: ~95% hit rate), instruction bytes return in 1-2 cycles. If miss, fetch from L2 or memory — 10-100+ cycles.
3. Instruction queue: Fetched instructions go into a buffer (the instruction queue or fetch buffer) awaiting decode. Modern CPUs fetch 4-8 instructions per cycle (16-32 bytes on x86 variable-length).
4. Branch prediction: The fetch unit uses the branch predictor to speculatively fetch down the predicted path, keeping the pipeline fed.

The L1 I-cache is critical — any stall here creates a pipeline bubble that out-of-order execution can partially hide but not eliminate. Instruction cache misses are expensive because they come in bursts (a branch misprediction can cause a cold fetch stream that evicts useful instructions).

A microcode control unit stores control words in a ROM/PROM called the control store. Each instruction triggers a sequence of micro-operations stored in microcode, which generates the control signals for datapath components. Microcode allows complex instructions to be implemented without additional hardware complexity—Intel's x86 uses microcode for instructions like ENTER and LOOP.

A hardwired control unit uses combinational logic (AND/OR gates, decoders) to generate control signals directly from the instruction opcode. It's faster (no microcode fetch decode) but more complex to design and modify. RISC processors typically use hardwired control for their simple instruction sets.

Modern processors often combine both: simple instructions are hardwired for speed, while complex instructions use microcode. This hybrid approach gets the performance benefit of hardwired control for common operations while retaining flexibility for compatibility with complex instruction sets.

Instruction-Level Parallelism (ILP) is the ability to execute multiple instructions simultaneously in a single clock cycle. It exists because processor stages are independent—instruction N+1 might not depend on instruction N's result.

Techniques to exploit ILP:

• Pipelining: Overlap execution of multiple instructions by dividing execution into stages. Classic RISC pipeline has 5 stages.
• Superscalar: Multiple execution units allow dispatching multiple instructions per cycle to different units.
• Out-of-order execution: Execute instructions in dataflow order rather than program order, filling gaps from cache misses.
• Speculative execution: Execute instructions before their outcome is known (branch prediction), discarding results if speculation fails.
• VLIW (Very Long Instruction Word): Compiler bundles independent instructions into a single long instruction word—the compiler does the scheduling.

The limits of ILP are reached when dependencies (data hazards) or branches prevent further parallelism—Amdahl's law governs the achievable speedup.

Modern CPUs support multiple privilege levels or security rings to isolate the operating system from user applications:

x86-64 ( rings):

• Ring 0 (kernel): Full hardware access, can execute all instructions, access all memory
• Ring 3 (user): Restricted instruction set, cannot access hardware directly, limited memory access via page tables
• Rings 1-2 rarely used (historical: DOS, Windows 3.1)

ARM64 (Exception Levels):

• EL0: User mode, least privilege
• EL1: Operating system kernel
• EL2: Hypervisor (for virtualization)
• EL3: Secure monitor (TrustZone)

Transitions between levels occur via specific instructions (SYSRET, ERET) or exceptions (interrupts, traps, page faults). Each level has different instruction availability and memory access rules enforced by the MMU.

The flags register (EFLAGS in x86, CPSR in ARM) stores condition codes that reflect the result of the most recent arithmetic or logical operation. Branch instructions read these flags to make decisions.

In x86:

• ZF (Zero Flag): Set when result is zero
• SF (Sign Flag): Set when result is negative (MSB=1)
• OF (Overflow Flag): Set on signed overflow
• CF (Carry Flag): Set on unsigned overflow

Branch instructions test these: JE (jump if equal = ZF=1), JL (jump if less = SF≠OF), JA (jump if above = CF=0 and ZF=0).

In ARM64, the flags are in the NZCV register (Negative, Zero, Carry, Overflow). Conditional instructions like csel (conditional select) can use these without branching, reducing branch misprediction penalties.

ARM64's cbz (compare and branch if zero) combines comparison and branch in one instruction, which is more efficient than separate cmp + b.eq.

Fixed-length encoding (used by most RISC: ARM, RISC-V, MIPS): All instructions are the same width (32 bits for ARM64, 32 bits for RISC-V base). This simplifies fetch and decode—the PC+4 always points to the next instruction.

Advantages: Simple pipeline, predictable timing, parallel decode of multiple instructions

Disadvantages: Wasteful for simple instructions, limits opcode space

Variable-length encoding (used by x86, x87, VAX): Instructions range from 1 to 15 bytes. The opcode might be in byte 1 or may require parsing a ModRM byte first.

Advantages: Dense code, more opcode space, can have very complex instructions

Disadvantages: Complex fetch (must determine length before knowing where next instruction starts), harder to decode in parallel

x86-64's complexity comes from this: the decoder must scan the instruction bytes to determine operand sizes, addressing modes, and instruction length. Modern x86 processors maintain a micro-op cache to hide this complexity from the pipeline.

Addressing modes specify how operands locate their data:

• Immediate: Value embedded in instruction. Use for constants known at compile time.
• Register direct: Value in a register. Most efficient—use for frequently accessed variables.
• Memory direct: Absolute address in instruction. Rarely used—hardcodes addresses that may not exist.
• Register indirect: Register contains address. Good for pointers: mov eax, [ebx].
• Base + offset: mov eax, [ebx+8]. Good for struct field access: ebx points to struct, 8 is field offset.
• Indexed: mov eax, [ebx+esi]. Good for array access: ebx=base, esi=index.
• Scaled indexed: mov eax, [ebx+esi*4]. For arrays of 4-byte elements: index already multiplied.
• PC-relative: Address relative to PC. Used for jumps and calls: b label in ARM is PC+offset.

ARM primarily supports immediate and register direct plus base+offset. x86 supports all these and more (including segment-relative in legacy modes). The complexity of addressing modes in x86 allows single-instruction memory operations that ARM would need multiple instructions for.

The stack is a LIFO (Last-In-First-Out) memory region used for function calls, local variables, and control flow. It's implemented via a dedicated register (SP/ESP/RSP on x86, SP on ARM) that points to the current top.

On x86-64:

• PUSH reg: SP -= 8, then store reg at [SP]
• POP reg: Load from [SP] into reg, then SP += 8
• CALL addr: Push return address (IP of instruction after CALL), then jump to addr
• RET: Pop return address into IP

The stack grows downward (toward lower addresses). Each function call pushes the return address and allocates space for locals. The frame pointer (BP/EBP/RBP) provides a stable reference point within each frame.

On ARM64, the stack pointer must maintain 16-byte alignment at call boundaries (AAPCS64 requirement). The STP (store pair) and LDP (load pair) instructions efficiently push/pop registers.

Stack overflow occurs when SP goes beyond the allocated stack region—detected by the OS causing a segmentation fault or stack overflow exception.

Big-endian: The most significant byte is stored at the lowest memory address. Like writing a number with the most significant digit first. Network protocols use big-endian (network byte order).

Little-endian: The least significant byte is stored at the lowest memory address. Like writing a number with the least significant digit first. Intel and AMD processors use little-endian.

Bi-endian: Can operate in either mode. ARM processors support both endianness via a mode bit (CPSR.E). They execute in little-endian by default but can switch. Some older architectures (MIPS, PowerPC) had bi-endian support.

Consider the 32-bit value 0x12345678 at address 0x100:

• Big-endian: 0x100=0x12, 0x101=0x34, 0x102=0x56, 0x103=0x78
• Little-endian: 0x100=0x78, 0x101=0x56, 0x102=0x34, 0x103=0x12

When transferring data between systems of different endianness, conversion is required. The htonl()/ntohl() functions on big-endian machines are no-ops, on little-endian machines they swap bytes.

The register file is the set of registers visible to the programmer (architectural registers) plus any internal registers used by the implementation.

Design trade-offs:

• Number of registers: More registers allow more simultaneous in-flight operations and reduce memory accesses, but increase the register file's cycle time and silicon area. ARM64 has 31 general-purpose registers; x86-64 has 16 (plus special registers).
• Port count: Reads require one port, writes require one port. A dual-ported register file can support two reads and one write per cycle. More ports enable superscalar execution but increase complexity and power.
• Read vs write latency: Register access takes 1 cycle typically. For critical paths, physical registers may be renamed and results forwarded directly to functional units without going through the register file.
• Width: 32-bit, 64-bit, or even 128-bit for SIMD. Larger registers enable vector operations but increase port count and power.

Register allocation pressure affects compiler code generation. If a function uses more registers than available, the compiler must spill to stack, which is slower.

Without branch prediction, a pipeline must wait until the branch instruction executes to know where to fetch next. This creates a bubble (stall) of several cycles for every branch.

Prediction allows the processor to guess the branch direction and continue fetching speculatively. If the guess is wrong, the pipeline is flushed and execution restarts from the correct path.

Main techniques:

• Static prediction: Always predict taken or not-taken. Simple but limited accuracy (~35-65%).
• 1-bit counter: Predict based on last outcome. Two states: branch-taken last time, branch-not-taken last time. Better but still limited.
• 2-bit counter: Requires two mispredictions to change prediction. More stable, better for loops. Four states: strongly taken, weakly taken, weakly not-taken, strongly not-taken.
• Two-level adaptive: Branch history table (BHT) tracks patterns for each branch address. Can recognize repeating patterns like alternating branches.
• Global branch history: A single global register (GHR) records the outcome of the last N branches. Correlates different branches.
• Perceptron branch predictor: Uses neural network-like weights to combine multiple history sources.

Modern predictors achieve 95-99% accuracy for typical workloads. The cost of a misprediction is 10-20 cycles (pipeline flush), so high accuracy is critical.

The datapath is the "muscle" of the CPU—the circuits that actually perform computation. It includes:

• Register file (read/write ports)
• ALU (arithmetic and logic operations)
• Multiplexers for selecting inputs
• buses that move data between components

The control unit is the "brain"—it generates the control signals that tell the datapath what to do. For each instruction, the control unit determines:

• Which registers to read
• Which ALU operation to perform
• Where to route the result
• Whether to update PC

The control unit's input is the instruction opcode (and sometimes status flags). Its output is a set of binary control signals that select MUX inputs, enable writes, and configure the ALU.

Design approaches:

• Hardwired: Combinational logic generates control signals from opcode. Fast but complex for complex ISAs.
• Microcoded: Control signals are stored in ROM and sequenced. More flexible for complex instructions but slower.

In super-scalar out-of-order processors, the control unit is more complex and includes the register rename unit, issue queue, and retirement logic.